Technical Field
The present invention relates to an integrated circuit (IC) layout, and more particularly, to a method for protecting an integrated circuit (IC) layout.
Description of Related Art
In general, the electronic circuit of an integrated circuit (IC) can be considered to be a graph of connected components such as transistors and resistors. Such an entity is commonly referred it as a netlist. Each component is mapped to one or more layout objects that are geometrical 2-dimensional objects such as, but not limited to, rectangles, polygons, and paths. In turn, these layout objects are used to define regions within the semiconductor die, which will receive different processing steps such as dopant, implants to produce N-type or P-type regions during the integrated circuit fabrication process.
Every layout object must satisfy manufacturing rules that specify geometrical requirements for each object as well as the relationship of an object to other objects. The manufacturing rules increase the probability that the final IC products will meet product specifications. Examples of such requirements include, but are not limited to, such items as minimum layout object width and minimum spacing from one layout object to that of another.
A circuit designer typically creates an IC design in the form of a netlist referencing circuit devices to be included in the IC and indicating which conductive net is to be connected to each device terminal. Design engineers typically use electronic design automation (EDA) applications to create IC layouts. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. A digital IC designer usually processes a netlist description of an IC using a placement and routing (P&R) tool that automatically generates an IC layout indicating the position and orientation of each device within the IC and indicating how conductors forming nets interconnecting device terminals are to be routed within the IC. When generating a layout for a digital IC, the P&R tool treats each device as a separate cell having a predetermined internal layout. The tool iteratively repositions cells and reroutes nets until it arrives at a layout solution satisfying constraints on the size and aspect ratio of the available layout area, on signal path delays, on net widths and spacing, and on power density and other constraints.
EDA applications create layouts from an IC netlist by various operations. Some of the physical design (PD) operations need to transform a netlist to a layout include: (1) placement which specifies the location of the IC components; (2) routing which generates the layout objects used to connect the IC components; (3) addition operations to complete the layout such as adding substrate/well contacts and power/ground routing. The result of the physical design process is an IC layout.
Advanced and emerging IC processes cannot reliably print arbitrary geometric patterns because of complex interactions between neighboring features during the patterning processes.
The development flow for the intellectual property (IP) block can be as wide and varied as the end system in which it might be used. There are different types of models provided to customers for integration purposes. These vary from high-level code, to library models, to layout that must be integrated and tested in the target system. This leads to a protection problem. In order to use an IP block effectively, you must be able to implement and verify that the behavior is what you expected it to be. For example, a design team inserts a core and then verifies that it works correctly.
IP that is needed for verification can be protected in a relatively straight forward manner. The EDA tool reads the IP and then verifies the design. This approach can be used by the various physical and logic verification tools that are typically found in a design process. Tools like Verilog or Spice simulators currently support this capability today. An IP provider can deliver a model that is protected and can be used by the design team.
When merging in hard IP, often times there can be mismatched layer information, physical incompatibilities at the edges resulting in DRC errors and performance degradation once the IP is in context and routes are made over the top. The need and selection of IP is important. It is believed that integration costs for external IP can be 2× or 3× the cost of IP, without taking the risk of failure into account. Still, companies are compelled to license and use external IP and successfully protect it in the flow so that it does not lose its value. However, no one solution will fit the many ways that IP can be protected, developed, delivered, and designed in.